WM5102 Datasheet, PDF (179/334 Pages) Wolfson Microelectronics plc – Audio Hub CODEC with Voice Processor DSP

Production Data
WM5102
JACK POP SUPPRESSION (MICDET CLAMP)
Under typical configuration of a 3.5mm headphone/accessory jack connection, there is a risk of pops
and clicks arising from jack insertion or removal. This can occur when the headphone load makes
momentary contact with the MICBIAS output when the jack is not fully inserted, as illustrated in Figure
63.
The WM5102 provides a MICDET Clamp function to suppress pops and clicks caused by jack
insertion or removal. The clamp is activated by a configurable logic function derived from external
logic inputs. The clamp status can be read using the relevant register status bit. The clamp status can
also be used to trigger an interrupt (IRQ) event or to trigger the Control Write Sequencer.
When the WM5102 is in the low-power Sleep mode, the MICDET Clamp function can be used as a
‘wake-up’ input; a typical use case is where an application is idle in standby mode until a headphone
or headset jack is inserted. This feature is enabled using the control bits described in Table 83 within
the “Low Power Sleep Configuration” section.
The MICDET Clamp function is controlled by a selectable logic condition, derived from the JD1 and/or
GP5 signals. The function is enabled and configured using the MICD_CLAMP_MODE register.
The JD1 signal is derived from the Jack Detect function (see Table 74). The GP5 signal is derived
from the GPIO5 input pin (see “General Purpose Input / Output”).
When the MICDET Clamp is active, the MICDET1/HPOUT1FB2 and HPOUT1FB1/MICDET2 pins are
short-circuited to GND. Note that both pins are shorted, regardless of the ACCDET_SRC register.
The configurable logic provides flexibility in selecting the appropriate conditions for activating the
MICDET Clamp. The clamp status can be read using the MICD_CLAMP_STS register.
The MICDET Clamp de-bounce is selected using the MICD_CLAMP_DB register, as described in
Table 75. Note that the de-bounce circuit uses the 32kHz clock, which must be enabled whenever
input de-bounce functions are required.
An Interrupt Request (IRQ) event is generated whenever the MICDET Clamp is asserted or de-
asserted (see “Interrupts”). Separate ‘mask’ bits are provided to enable IRQ events on the rising
and/or falling edge of the MICDET Clamp status.
The Control Write Sequencer can be triggered by the MICDET Clamp status. This is enabled using
register bits described in the “Low Power Sleep Configuration” section.
The MICDET Clamp function is illustrated in Figure 63. Note that the jack plug is shown partially
removed, with the MICDET1 pin in contact with the headphone load.
Figure 63 MICDET Clamp circuit
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PD, June 2014, Rev 4.2
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