WM5102 Datasheet, PDF (151/334 Pages) Wolfson Microelectronics plc – Audio Hub CODEC with Voice Processor DSP

Production Data
WM5102
SLIMBUS CLOCKING CONTROL
The clock frequency of the SLIMbus interface is not fixed, and may be set according to the application
requirements. The clock frequency can be reconfigured dynamically as required.
The WM5102 SLIMbus interface includes a Framer Device. When configured as the active Framer,
the SLIMbus clock (SLIMCLK) is an output from the WM5102. At other times, SLIMCLK is an input.
The Framer function can be transferred from one device to another; this is known as Framer
Handover, and is controlled by the Manager Device.
The supported Root Frequencies in Active Framer mode are 24.576MHz or 22.5792MHz only. At
other times, the supported Root Frequencies are as defined in the MIPI Alliance specification for
SLIMbus.
Under normal operating conditions, the SLIMbus interface operates with a fixed Root Frequency (RF);
dynamic updates to the bus rate are applied using a selectable Clock Gear (CG) function. The Root
Frequency and the Clock Gear setting are controlled by the Manager Device; these parameters are
transmitted in every SLIMbus superframe to all devices on the bus.
In Gear 10 (the highest Clock Gear setting), the SLIMCLK input (or output) frequency is equal to the
Root Frequency. In lower gears, the SLIMCLK frequency is reduced by increasing powers of 2.
The Clock Gear definition is shown in Table 56. Note that 24.576MHz Root Frequency is an example
only; other frequencies are also supported.
CLOCK GEAR
DESCRIPTION
10
Divide by 1
9
Divide by 2
8
Divide by 4
7
Divide by 8
6
Divide by 16
5
Divide by 32
4
Divide by 64
3
Divide by 128
2
Divide by 256
1
Divide by 512
Table 56 SLIMbus Clock Gear Selection
SLIMCLK FREQUENCY
(assuming 24.576MHz Root Frequency)
24.576MHz
12.288MHz
6.144MHz
3.072MHz
1.536MHz
768kHz
384kHz
192kHz
96kHz
48kHz
When the WM5102 is the active Framer, the SLIMCLK output is synchronised to the SYSCLK or
ASYNCCLK system clock, as selected by the SLIMCLK_SRC register bit.
The applicable system clock must be enabled, and configured at the SLIMbus Root Frequency,
whenever the WM5102 is the active Framer. See “Clocking and Sample Rates” for details of the
SYSCLK and ASYNCCLK system clocks.
When the WM5102 is not configured as the active Framer device, then the SLIMCLK input can be
used to provide a reference source for the Frequency Locked Loops (FLLs). The frequency of this
reference is controlled using the SLIMCLK_REF_GEAR register, as described in Table 57.
The SLIMbus clock reference is generated using an adaptive divider on the SLIMCLK input. The
divider automatically adapts to the SLIMbus Clock Gear (CG).
Note that, if the Clock Gear (CG) on the bus is lower than the SLIMCLK_REF_GEAR, then the
selected reference frequency cannot be supported, and the SLIMbus clock reference is disabled.
The SLIMbus clock reference is selected as input to the FLLs using the FLLn_REFCLK_SRC
registers. See “Clocking and Sample Rates” for details of system clocking and the FLLs.
w
PD, June 2014, Rev 4.2
151