WM5102 Datasheet, PDF (119/334 Pages) Wolfson Microelectronics plc – Audio Hub CODEC with Voice Processor DSP

Production Data
WM5102
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
LRCLK
BCLK
RXDAT/
TXDAT
LEFT CHANNEL
1/fs
RIGHT CHANNEL
1
2
MSB
3
n-2 n-1 n
Input Word Length (WL)
LSB
1
2
3
n-2 n-1 n
Figure 48 Left Justified Data Format (assuming n-bit word length)
AIF TIMESLOT CONFIGURATION
Digital audio interface AIF1 supports multi-channel operation; up to 8 input (RX) channels and 8
output (TX) channels can be supported simultaneously. A high degree of flexibility is provided to
define the position of the audio samples within each LRCLK frame; the audio channel samples may
be arranged in any order within the frame.
AIF2 and AIF3 also provide flexible configuration options, but support only 1 stereo input and 1 stereo
output pair each.
Note that, on each interface, all input and output channels must operate at the same sample rate (fs).
Each of the audio channels can be enabled or disabled independently on the transmit (TX) and
receive (RX) signal paths. For each enabled channel, the audio samples are assigned to one timeslot
within the LRCLK frame.
In DSP modes, the timeslots are ordered consecutively from the start of the LRCLK frame. In I2S and
Left-Justified modes, the even-numbered timeslots are arranged in the first half of the LRCLK frame,
and the odd-numbered timeslots are arranged in the second half of the frame.
The timeslots are assigned independently for the transmit (TX) and receive (RX) signal paths. There is
no requirement to assign every available timeslot to an audio sample; some slots may be unused, if
desired. Care is required, however, to ensure that no timeslot is allocated to more than one audio
channel.
The number of BCLK cycles within a slot is configurable; this is the Slot Length. The number of valid
data bits within a slot is also configurable; this is the Word Length. The number of BCLK cycles per
LRCLK frame must be configured; it must be ensured that there are enough BCLK cycles within each
LRCLK frame to transmit or receive all of the enabled audio channels.
Examples of the AIF Timeslot Configurations are illustrated in Figure 49 to Figure 52. One example is
shown for each of the four possible data formats.
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PD, June 2014, Rev 4.2
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