WM5102 Datasheet, PDF (111/334 Pages) Wolfson Microelectronics plc – Audio Hub CODEC with Voice Processor DSP

Production Data
WM5102
DSP FIRMWARE CONTROL
The WM5102 digital core incorporates a programmable DSP block, capable of running a wide range
of audio enhancement functions. Different firmware configurations can be loaded onto the DSP,
enabling the WM5102 to be highly customised for specific application requirements.
The programmable DSP is ideally suited to Voice processing algorithms such as TX/RX path noise
reduction, and Acoustic Echo Cancellation (AEC). Further applications for the DSP include signal
enhancements such as Virtual Surround Sound (VSS) or Multiband Compressor (MBC). Note that it is
possible to implement more than one type of audio enhancement function on the DSP; the precise
combination(s) of functions will vary from one firmware configuration to another.
DSP firmware can be configured using Wolfson-supplied software packages. A software programming
guide can also be provided to assist users in developing their own software algorithms - please
contact your local Wolfson representative for further information.
In order to use the DSP, the required firmware configuration must first be loaded onto the device by
writing the appropriate files to the WM5102 register map. The firmware configuration will comprise
Program, Coefficient and Data content. In some cases, the Coefficient content must be derived using
tools provided in Wolfson’s WISCE™ evaluation board control software.
Details of how to load the firmware configuration onto the WM5102 are described below. Note that the
WISCE™ evaluation board control software provides support for easy loading of Program, Coefficient
and Data content onto the WM5102. Please contact your local Wolfson representative for more details
of the WISCE™ evaluation board control software.
After loading the DSP firmware, the DSP functions must be enabled using the associated register
control fields.
The audio signal paths connecting to/from the DSP are configured as described in the “Digital Core”
section. Note that the DSP firmware must be loaded and enabled before audio signal paths can be
enabled.
DSP FIRMWARE MEMORY CONTROL
The DSP firmware memory is programmed by writing to the registers referenced in Table 24. Note
that the DSP clock must be configured and enabled to support read/write access to these registers.
The WM5102 Program, Coefficient and Data memory space is described in Table 24. See “Register
Map” for a definition of these register addresses.
The Program firmware parameters are formatted as 40-bit words. For this reason, 3 x 16-bit register
addresses are required for each 40-bit word.
The Coefficient and Data firmware parameters are formatted as 24-bit words. For this reason, 2 x 16-
bit register addresses are required for each 24-bit word.
DESCRIPTION
REGISTER ADDRESS
DSP1
Program memory
10_0000h to 10_5FFFh
(24576 registers)
Coefficient memory
18_0000h to 18_07FFh
(2048 registers)
X Data memory
19_0000h to 19_47FFh
(18432 registers)
Y Data memory
1A_8000h to 1A_97FFh
(6144 registers)
Table 24 DSP Program, Coefficient and Data Registers
DSP MEMORY SIZE
8192 x 40-bit words
1024 x 24-bit words
9216 x 24-bit words
3072 x 24-bit words
Clocking is required for any functionality of the DSP, including any register read/write operations
associated with DSP firmware loading.
The clock source for the DSP is derived from SYSCLK, which must also be enabled. See “Clocking
and Sample Rates” for details of how to configure SYSCLK.
The DSP clock frequency is selected using the DSP1_CLK_SEL register. The DSP clock frequency
must be less than or equal to the SYSCLK frequency.
If the SUBSYS_MAX_FREQ bit is set to ‘0’, then the DSP clock frequency is restricted to a maximum
of 24.576MHz (or 22.5792MHz), even if a higher rate is selected. The SUBSYS_MAX_FREQ should
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PD, June 2014, Rev 4.2
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