WM5102 Datasheet, PDF (125/334 Pages) Wolfson Microelectronics plc – Audio Hub CODEC with Voice Processor DSP

Production Data
WM5102
REGISTER
ADDRESS
BIT
LABEL
5 AIF2_BCLK_MST
R
R1345
(0541h)
AIF2 Tx
Pin Ctrl
3 AIF2TX_LRCLK_
SRC
2 AIF2TX_LRCLK_I
NV
1 AIF2TX_LRCLK_
FRC
0 AIF2TX_LRCLK_
MSTR
R1346
(0542h)
AIF2 Px
Pin Ctrl
2 AIF2RX_LRCLK_
INV
1 AIF2RX_LRCLK_
FRC
0 AIF2RX_LRCLK_
MSTR
Table 30 AIF2 Master / Slave Control
DEFAULT
DESCRIPTION
0
AIF2 Audio Interface BCLK Master Select
0 = AIF2BCLK Slave mode
1 = AIF2BCLK Master mode
1
AIF2 Audio Interface TX path LRCLK
Select
0 = AIF2TXLRCLK
1 = AIF2RXLRCLK
Note that the TXLRCLK function, when
used, must be configured on a GPIO pin.
0
AIF2 Audio Interface TX path LRCLK
Invert
0 = AIF2TXLRCLK not inverted
1 = AIF2TXLRCLK inverted
0
AIF2 Audio Interface TX path LRCLK
Output Control
0 = Normal
1 = AIF2TXLRCLK always enabled in
Master mode
0
AIF2 Audio Interface TX path LRCLK
Master Select
0 = AIF2TXLRCLK Slave mode
1 = AIF2TXLRCLK Master mode
0
AIF2 Audio Interface LRCLK Invert
0 = AIF2RXLRCLK not inverted
1 = AIF2RXLRCLK inverted
0
AIF2 Audio Interface LRCLK Output
Control
0 = Normal
1 = AIF2RXLRCLK always enabled in
Master mode
0
AIF2 Audio Interface LRCLK Master
Select
0 = AIF2RXLRCLK Slave mode
1 = AIF2RXLRCLK Master mode
REGISTER
ADDRESS
R1408
(0580h)
AIF3
BCLK Ctrl
R1409
(0581h)
AIF3 Tx
Pin Ctrl
BIT
LABEL
7 AIF3_BCLK_INV
6 AIF3_BCLK_FRC
5 AIF3_BCLK_MST
R
3 AIF3TX_LRCLK_
SRC
DEFAULT
DESCRIPTION
0
AIF3 Audio Interface BCLK Invert
0 = AIF3BCLK not inverted
1 = AIF3BCLK inverted
0
AIF3 Audio Interface BCLK Output Control
0 = Normal
1 = AIF3BCLK always enabled in Master
mode
0
AIF3 Audio Interface BCLK Master Select
0 = AIF3BCLK Slave mode
1 = AIF3BCLK Master mode
1
AIF3 Audio Interface TX path LRCLK
Select
0 = AIF3TXLRCLK
1 = AIF3RXLRCLK
Note that the TXLRCLK function, when
used, must be configured on a GPIO pin.
w
PD, June 2014, Rev 4.2
125