W83194R-67B Datasheet, PDF (9/18 Pages) Winbond – 100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67B
8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit
@PowerUp Pin
Description
7
1
- Reserved
6
1
7 PCICLK_F (Active / Inactive)
5
1
- Reserved
4
1
13 PCICLK4 (Active / Inactive)
3
1
12 PCICLK3 (Active / Inactive)
2
1
11 PCICLK2 (Active / Inactive)
1
1
10 PCICLk1 (Active / Inactive)
0
1
8 PCICLK0 (Active / Inactive)
8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit
@PowerUp
Pin
Description
7
1
-
Reserved
6
x
-
Latched FS0#
5
1
26
48MHz (Active / Inactive)
4
1
25
24MHz (Active / Inactive)
3
1
39
SDRAM_F(Active / Inactive)
2
1
21,20,18,17 SDRAM(8:11) (Active / Inactive)
1
1
32,31,29,28 SDRAM(4:7) (Active / Inactive)
0
1
38,37,35,34 SDRAM(0:3) (Active / Inactive)
8.3.5 Register 4: Reserved Register (1 = Active, 0 = Inactive)
Bit
@PowerUp Pin
Description
7
1
- Reserved
6
1
- Reserved
5
1
- Reserved
4
1
- Reserved
3
x
- Latched FS1#
2
1
- Reserved
1
x
- Latched FS3#
0
1
- Reserved
PRELIMINARY
Publication Release Date: Dec.. 1999
-9-
Revision 0.50