W83194R-67B Datasheet, PDF (8/18 Pages) Winbond – 100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67B
Frequency table by I2C
SSEL3 SSEL2 SSEL1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
SSEL0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
CPU,SDRA
M(MHz)
60
66.8
70
90
97.0
80
83.3
95.25
100.2
75
80
83.3
105
110
115
124
133
PCI(MHz)
30(CPU/2)
33.4(CPU/2)
35(CPU/2)
30(CPU/3)
32.33(CPU/3)
26.67(CPU/3)
27.77(CPU/3)
31.75(CPU/3)
33.3(CPU/3)
37.5(CPU/2)
40(CPU/2)
41.65(CPU/2)
35(CPU/3)
36.67(CPU/3)
38.33(CPU/3)
31(CPU/4)
33.3(CPU/4)
PRELIMINARY
REF,IOAPIC (MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit
@PowerUp Pin
Description
7
x
- Latched FS2#
6
1
- 0 = 0.5% down type spread, overrides Byte0-bit7.
1= Center type spread.
5
1
- Reserved
4
1
- Reserved
3
1
42 CPUCLK2 (Active / Inactive)
2
1
43 CPUCLK1 (Active / Inactive)
1
1
45 CPUCLK0 (Active / Inactive)
0
1
46 CPUCLK_F (Active / Inactive)
Publication Release Date: Dec.. 1999
-8-
Revision 0.50