W83194R-67B Datasheet, PDF (3/18 Pages) Winbond – 100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67B
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
5.1 Crystal I/O
SYMBOL
PIN
Xin
4
Xout
5
PRELIMINARY
I/O
IN
OUT
FUNCTION
Crystal input with internal loading capacitors and
feedback resistors.
Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
CPUCLK_F
CPUCLK[0:2]
*CPU_STOP#
SDRAM_F
SDRAM [ 0:11]
PCICLK_F/
*MODE
PCICLK0/*FS3
PCICLK [ 1:4 ]
BUFFER IN
PIN
I/O
FUNCTION
46
45,43,42
41
39
17,18,20,21,28
,29,31,32,34,
35,37,38
7
8
10,11,12,13
OUT
OUT
IN
OUT
OUT
I/O
I/O
OUT
Free running CPU clock. Not affected by
CPU_STOP#
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Powered by VddL2. Low if CPU_STOP# is low.
This asynchronous input halts CPUCLK[0:2] and
SDRAM(0:11) at logic level when driven low.
Free running SDRAM clock. Not affected by
CPU_STOP#
SDRAM clock outputs. Fanout buffer outputs from
BUFFER IN pin.(Controlled by chipset)
Free running PCI clock during normal operation.
Latched Input. Mode=1, Pin 2 is REF0; Mode=0,
Pin2 is PCI_STOP#
Low skew (< 250ps) PCI clock outputs.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs. Synchronous
to CPU clocks with 1/-4ns skew(CPU early).
15
IN Inputs to fanout for SDRAM outputs.
Publication Release Date: Dec.. 1999
-3-
Revision 0.50