W83194R-67B Datasheet, PDF (15/18 Pages) Winbond – 100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67B
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
1
2
3
4
PRELIMINARY
1
2
3
4
CPUCLK[0:3]
SDRAM
For synchronous Chipset, CPU_STOP# pin is an asynchronous “ active low ” input pin used to stop
the CPU clocks for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU ?locks on latency“ is less than 4 CPU clocks and
?locks off latency” is less then 4 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
PCI_STOP#
1
2
1
2
PCICLK[0:5]
For synchronous Chipset, PCI_STOP# pin is an asynchronous ?ctive low” input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output
with full pulse width. In this case, PCI ?locks on latency“ is less than 2 PCI clocks and ?locks off
latency” is less then 2 PCI clocks.
- 15 -
Publication Release Date: Dec.. 1999
Revision 0.50