W79E548 Datasheet, PDF (9/79 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E548/W79L548
Timers
The W79E(L)548 has three 16-bit timers that are functionally similar to the timers of the 8052 family.
When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing
the user with the option of operating in a mode that emulates the timing of the original 8052. The
W79E(L)548 has an additional feature, the watchdog timer. This timer is used as a System Monitor or
as a very long time period timer.
Interrupts
The Interrupt structure in the W79E(L)548 is slightly different from that of the standard 8052. Due to
the presence of additional features and peripherals, the number of interrupt sources and vectors has
been increased. The W79E(L)548 provides 7 interrupt resources with two priority level, including 2
external interrupt sources, timer interrupts, serial I/O interrupts.
Power Management
Like the standard 80C52, the W79E(L)548 also has IDLE and POWER DOWN modes of operation. In
the IDLE mode, the clock to the CPU core is stopped while the timers, serial port and interrupts clock
continue to operate. In the POWER DOWN mode, all the clock are stopped and the chip operation is
completely stopped. This is the lowest power consumption state.
On-chip Data SRAM
The W79E(L)548 has 1K Bytes of data space SRAM which is read/write accessible and is memory
mapped. This on-chip MOVX SRAM is reached by the MOVX instruction. It is not used for executable
program memory. There is no conflict or overlap among the 256 bytes Scratchpad RAM and the 1K
Bytes MOVX SRAM as they use different addressing modes and separate instructions. The on-chip
MOVX SRAM is enabled by setting the DME0 bit in the PMR register. After a reset, the DME0 bit is
cleared such that the on-chip MOVX SRAM is disabled, and all data memory spaces 0000H − FFFFH
access to the external memory.
7. MEMORY ORGANIZATION
The W79E(L)548 separates the memory into two separate sections, the Program Memory and the
Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory
is used to store data or for memory mapped devices.
Program Memory
The Program Memory on the standard 8052 can only be addressed to 64 Kbytes long. By invoking the
banking methodology, W79E(L)548 can extend to two 64KB flash EPROM banks, APFlash0 and
APFlash1. There are on-chip ROM banks which can be used similarly to that of the 8052. All
instructions are fetched for execution from this memory area. The MOVC instruction can also access
this memory region. There is an auxiliary 4KB Flash EPROM bank (LDFlash) resided user loader
program for In-System Programming (ISP). Both APFlashs allow serial or parallel download according
to user loader program in LDFlash.
Publication Release Date: December 12, 2005
-9-
Revision A1