W79E548 Datasheet, PDF (21/79 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E548/W79L548
ROM Banking Control
Bit:
7
6
5
4
3
2
1
0
-
-
-
- EN128K DCP12 DCP11 DCP10
Mnemonic: ROMCON
Address: ABh
EN128K: On-chip ROM banking enable. Set this bit to enable APFlash0 and APFlash1 by banking
mechanism. The P1.x is selected to be the auxiliary highest address line A16.
DCP1x: A16 selection. By default, P1.7 is defined as A16.
A16
DCP12
DCP11
DCP10
P1.0
0
0
0
P1.1
0
0
1
P1.2
0
1
0
P1.3
0
1
1
P1.4
1
0
0
P1.5
1
0
1
P1.6
1
1
0
P1.7
1
1
1
ISP Address Low Byte
Bit:
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Mnemonic: SFRAL
Address: ACh
Low byte destination address for In System Programming operation. SFRAH and SFRAL address a
specific ROM byte for erasure, programming or read.
ISP Address High Byte
Bit:
7
6
5
4
3
2
1
0
A15 A14 A13 A12 A11 A10
A9
A8
Mnemonic: SFRAH
Address: ADh
High byte destination address for In System Programming operation. SFRAH and SFRAL address a
specific ROM byte for erasure, programming or read.
ISP Data Buffer
Bit:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Mnemonic: SFRFD
Address: AEh
In ISP mode, read/write a specific byte ROM content must go through SFRFD register.
ISP Operation Modes
Bit:
7
6
5
BANK WFWIN NOE
4
3
2
1
0
NCE CTRL3 CTRL2 CTRL1 CTRL0
Mnemonic: SFRCN
Address: AFh
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Publication Release Date: December 12, 2005
Revision A1