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W79E548 Datasheet, PDF (68/79 Pages) Winbond – 8-BIT MICROCONTROLLER
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W79E548/W79L548
18.3.2 MOVX Characteristics Using Strech Memory Cycle
PARAMETER
SYMBOL
Data Access ALE Pulse Width
Address Hold After ALE Low for
MOVX write
RD Pulse Width
tLLHL2
tLLAX2
tRLRH
WR Pulse Width
tWLWH
RD Low to Valid Data In
Data Hold after Read
Data Float after Read
tRLDV
tRHDX
tRHDZ
ALE Low to Valid Data In
tLLDV
Port 0 Address to Valid Data In
tAVDV1
ALE Low to RD or WR Low
Port 0 Address to RD or WR
Low
tLLWL
tAVWL
VARIABLE
CLOCK
MIN.
1.5tCLCL - 5
2.0tCLCL - 5
0.5tCLCL - 5
2.0tCLCL - 5
tMCS - 10
2.0tCLCL - 5
tMCS - 10
0
0.5tCLCL - 5
1.5tCLCL - 5
tCLCL - 5
2.0tCLCL - 5
VARIABLE
CLOCK
MAX.
UNITS STRECH
nS
tMCS = 0
tMCS>0
nS
nS
nS
2.0tCLCL - 20
nS
tMCS - 20
nS
tCLCL - 5
nS
2.0tCLCL - 5
2.5tCLCL - 5
nS
tMCS + 2tCLCL - 40
3.0tCLCL - 20
nS
2.0tCLCL - 5
0.5tCLCL + 5
nS
1.5tCLCL + 5
nS
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
Port 2 Address to RD or WR
Low
tAVWL2
1.5tCLCL - 5
2.5tCLCL - 5
nS
tMCS = 0
tMCS>0
Data Valid to WR Transition
Data Hold after Write
tQVWX
tWHQX
-5
1.0tCLCL - 5
tCLCL - 5
2.0tCLCL - 5
nS
tMCS = 0
tMCS>0
nS
tMCS = 0
tMCS>0
RD Low to Address Float
tRLAZ
0.5tCLCL - 5
nS
RD or WR high to ALE high
tWHLH
0
1.0tCLCL - 5
10
1.0tCLCL + 5
nS
tMCS = 0
tMCS>0
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of tMCS
for each selection of the Stretch value.
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