W79E548 Datasheet, PDF (35/79 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E548/W79L548
Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.
When the W79E(L)548 is exiting from an Idle mode with a reset, the instruction following the one
which put the device into Idle mode is not executed. So there is no danger of unexpected writes.
Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the device goes into Power Down mode. In the
Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The W79E(L)548 will exit the Power Down mode with a reset or by an external interrupt pin enabled
as level detect. An external reset can be used to exit the Power down state. The high on RST pin
terminates the Power Down mode, and restarts the clock. The program execution will restart from
0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
The W79E(L)548 can be woken from the Power Down mode by forcing an external interrupt pin
activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and
the external input has been set to a level detect mode. If these conditions are met, then the low level
on the external pin re-starts the oscillator. Then device executes the interrupt service routine for the
corresponding external interrupt. After the interrupt service routine is completed, the program
execution returns to the instruction after the one which put the device into Power Down mode and
continues from there.
Table 5. Status of external pins during Idle and Power Down
MODE
PROGRAM
MEMORY
ALE
Idle
Internal
1
Idle
External
1
Power Down
Internal
0
Power Down External
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
Reset Conditions
The user has several hardware related options for placing the W79E(L)548 into reset condition. In
general, most register bits go to their reset value irrespective of the reset condition, but there are a few
flags whose state depends on the source of reset. The user can use these flags to determine the
cause of reset using software. There are two ways of putting the device into reset state. They are
External reset and Watchdog reset.
External Reset
The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST
pin must be held for at least 2 machine cycles to ensure detection of a valid RST high. The reset
circuitry then synchronously applies the internal reset signal. Thus the reset is a synchronous
operation and requires the clock to be running to cause an external reset.
- 35 -
Publication Release Date: December 12, 2005
Revision A1