W79E548 Datasheet, PDF (34/79 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E548/W79L548
CLK
ALE
PSEN
WR
PORT 0
PORT 2
Last Cycle
of Previous
Instruction
First
Machine Cycle
Second
Machine Cycle
Third
Machine Cycle
MOVX instruction cycle
Fourth
Machine Cycle
Next
Instruction
Machine Cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
A0-A7
D0-D7 A0-A7
D0-D7 A0-A7
MOVX Inst.
Address
Next Inst.
Address
MOVX Data
Address
MOVX Inst.
Next Inst.
Read
A15-A8
A15-A8
D0-D7
MOVX Data out
A15-A8
A0-A7
D0-D7
A15-A8
Figure 10. Data Memory Write with Stretch Value = 2
9. POWER MANAGEMENT
The W79E(L)548 has several features that help the user to control the power consumption of the
device. The power saving features are basically the POWER DOWN mode and the IDLE mode of
operation.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer and Serial port
blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program
Status Word, the Accumulator and the other registers hold their contents. The ALE and PSEN pins are
held high during the Idle state. The port pins hold the logical states they had at the time Idle was
activated. The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the
activation of any enabled interrupt can wake up the processor. This will automatically clear the Idle bit,
terminate the Idle mode, and the Interrupt Service Routine(ISR) will be executed. After the ISR,
execution of the program will continue from the instruction which put the device into Idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either by
applying a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The
external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be
recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is already running there is no delay and execution
starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out
will cause a watchdog timer interrupt which will wake up the device. The software must reset the
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