W83176R-732_06 Datasheet, PDF (8/12 Pages) Winbond – 2 DIMM DDR ZERO DELAY buffer for Sis chipset

W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
8. SPECIFICATIONS
8.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused
inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
SYMBOL
PARAMETER
RATING
VDD, AVDD
Voltage on any pin with respect to GND
- 0.5 V to + 3.6 V
T_STG
T_B
T_A
Storage Temperature
Ambient Temperature
Operating Temperature
- 65°C to + 150°C
- 55°C to + 125°C
0°C to + 70°C
8.2 AC CHARACTERISTICS
VDD = AVDD = 2.5V ± 5 %, T_A = 0°C to +70°C, Test load = 10 pF
PARAMETER
SYMBOL MIN
TYP
MAX
UNIT
S
Operating clock
frequency
F_IN
100
200 MHz
Input Clock Duty Cycle
Dtin
40
60
%
Dynamic Supply Current Idd
300
mA
Cycle to Cycle Jitter
C-Cjitter
200
ps
Output to Output Skew Tskew
100
ps
Output clock Rise time
Tor
650
950
ps
Output clock Fall time
Tof
650
950
ps
Output clock Duty Cycle Dtot
45
55
%
Output differential-pair
crossing voltag
Voc
(Vdd/2)
-0.2
Vdd/2
(Vdd/2)
+ 0.2
V
TEST CONDITIONS
Fin=100 to 200Mhz
Fout=100 to 200Mhz
Fout=100 to 200Mhz
Fout=100 to 200Mhz
Fout=100 to 200Mhz
Fout=100 to 200Mhz
Fout=100 to 200Mhz
-5-
Publication Release Date: March, 2006
Revision 1.1