W83176R-732_06 Datasheet, PDF (4/12 Pages) Winbond – 2 DIMM DDR ZERO DELAY buffer for Sis chipset

W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
1. GENERAL DESCRIPTION
The W83176R-732 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS chipset. W83176R-
732 can support 2 D.D.R. DRAM DIMMs.
The W83176R-732 provides I²C serial bus interface to program the registers to enable or disable each
clock outputs. The W83176R-732 accepts a reference clock as its input and runs on 2.5V supply.
2. PRODUCT FEATURES
• Zero-delay clock outputs
• Feedback pins for synchronous
• Supports up to 2 D.D.R. DIMMs
• One pairs of additional outputs for feedback
• Low Skew outputs (< 100ps)
• Supports 400MHz D.D.R. SDRAM
• I²C 2-Wire serial interface and supports Byte or Block Date RW
• 28-pin SSOP package
3. PIN CONFIGURATION
*: Internal pull-up resistor 120K to VDD
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Publication Release Date: March, 2006
Revision 1.1