W83176R-732_06 Datasheet, PDF (5/12 Pages) Winbond – 2 DIMM DDR ZERO DELAY buffer for Sis chipset

W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET
4. BLOCK DIAGRAM
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL
IN
OUT
I/O
*
NC
Input
Output
Bi-directional Pin
Internal 120kΩ pull-up
Not connect
DESCRIPTION
5.1 Clock Outputs
PIN
27,25,16,14,5,1
26,24,17,13,4,2
PIN NAME
CLKC [5:0]
CLKT [5:0]
22
SDATA *
7
8
9,18,21
19
SCLK *
CLK_INT
N/C
FB_OUTT
20
FB_INT
TYPE
DESCRIPTION
OUT Complementary Clocks of differential pair outputs
OUT
I/O
IN
True Clocks of differential pair outputs
Serial data of I²C 2-wire control interface
Internal pull-up resistor 120K to Vdd
Serial clock of I²C 2-wire control interface
Internal pull-up resistor 120K to Vdd
IN True reference clock input, 3.3V tolerant input
NC Not connected
True Feedback output, dedicated for external feedback. It
OUT switches at the same frequency as the CLK. This output
must be wired to FB_INT.
True Feedback input, provides feedback signal to the
IN internal PLL for synchronization with CLK_INT to
eliminate phase error.
-2-