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W77LE532_07 Datasheet, PDF (76/88 Pages) Winbond – 8-BIT MICROCONTROLLER
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W77LE532/W77L532A
MOVX CHARACTERISTICS USING STRECH MEMORY CYCLES
PARAMETER
Data Access ALE Pulse Width
Address Hold After ALE Low for
MOVX write
RD Pulse Width
WR Pulse Width
SYMBOL
tLLHL2
tLLAX2
tRLRH
tWLWH
VARIABLE
CLOCK MIN.
1.5tCLCL - 5
2.0tCLCL - 5
0.5tCLCL - 5
2.0tCLCL - 5
tMCS - 10
2.0tCLCL - 5
tMCS - 10
RD Low to Valid Data In
tRLDV
Data Hold after Read
tRHDX
0
Data Float after Read
tRHDZ
ALE Low to Valid Data In
tLLDV
Port 0 Address to Valid Data In
ALE Low to RD or WR Low
Port 0 Address to RD or WR
Low
tAVDV1
tLLWL
tAVWL
0.5tCLCL - 5
1.5tCLCL - 5
tCLCL - 5
2.0tCLCL - 5
VARIABLE
CLOCK MAX.
2.0tCLCL - 20
tMCS - 20
tCLCL - 5
2.0tCLCL - 5
2.5tCLCL - 5
tMCS + 2tCLCL - 40
3.0tCLCL - 20
2.0tCLCL - 5
0.5tCLCL + 5
1.5tCLCL + 5
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
STRECH
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
tMCS = 0
tMCS>0
Port 2 Address to RD or WR
Low
tAVWL2
1.5tCLCL - 5
2.5tCLCL - 5
nS
tMCS = 0
tMCS>0
Data Valid to WR Transition
Data Hold after Write
tQVWX
tWHQX
-5
1.0tCLCL - 5
tCLCL - 5
2.0tCLCL - 5
nS
tMCS = 0
tMCS>0
nS
tMCS = 0
tMCS>0
RD Low to Address Float
tRLAZ
0.5tCLCL - 5
nS
RD or WR high to ALE high
tWHLH
0
1.0tCLCL - 5
10
1.0tCLCL + 5
nS
tMCS = 0
tMCS>0
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of tMCS
for each selection of the Stretch value.
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