W77LE532_07 Datasheet, PDF (42/88 Pages) Winbond – 8-BIT MICROCONTROLLER

W77LE532/W77L532A
The selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching
to divide by 64 or 1024 mode must first go from divide by 4 mode. This means software can not switch
directly between clock/64 and clock/1024 mode. The CPU has to return clock/4 mode first, then go to
clock/64 or clock/1024 mode.
In Economy mode, the serial port can not receive/transmit data correctly because the baud rate is
changed. In some systems, the external interrupts may require the fastest process such that the
reducing of operating speed is restricted. In order to solve these dilemmas, the W77L532 offers a
switchback feature which allows the CPU back to clock/4 mode immediately when triggered by serial
operation or external interrupts. The switchback feature is enabled by setting the SWB bit (PMR.5). A
serial port reception/transmission or qualified external interrupt which is enabled and acknowledged
without block conditions will cause CPU to return to divide by 4 mode. For the serial port reception, a
switchback is generated by a falling edge associated with start bit if the serial port reception is
enabled. When a serial port transmission, an instruction which writes a byte of data to serial port
buffer will cause a switchback to ensure the correct transmission. The switchback feature is
unaffected by serial port interrupt flags. After a switchback is generated, the software can manually
return the CPU to Economy mode. Note that the modification of clock control bits CD0 and CD1 will be
ignored during serial port transmit/receive when switchback is enabled. The Watchdog timer reset,
power-on/fail reset or external reset will force the CPU to return to divide by 4 mode.
Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the device goes into Power Down mode. In the
Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The W77L532 will exit the Power Down mode with a reset or by an external interrupt pin enabled as
level detect. An external reset can be used to exit the Power down state. The high on RST pin
terminates the Power Down mode, and restarts the clock. The program execution will restart from
0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
The W77L532 can be woken from the Power Down mode by forcing an external interrupt pin
activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and
the external input has been set to a level detect mode. If these conditions are met, then the low level
on the external pin re-starts the oscillator. Then device executes the interrupt service routine for the
corresponding external interrupt. After the interrupt service routine is completed, the program
execution returns to the instruction after the one which put the device into Power Down mode and
continues from there.
Table 5. Status of external pins during Idle and Power Down
MODE
PROGRAM
MEMORY
ALE
Idle
Internal
1
Idle
External
1
Power Down Internal
0
Power Down External
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
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