W77LE532_07 Datasheet, PDF (27/88 Pages) Winbond – 8-BIT MICROCONTROLLER

W77LE532/W77L532A
SPRA0: Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It
is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1
will be ignored when this bit is set to 1 and SWB = 1.
TIMED ACCESS
Bit:
7
TA.7
6
TA.6
5
TA.5
4
TA.4
3
TA.3
2
TA.2
1
TA.1
0
TfA.0
Mnemonic: TA
Address: C7h
TA: The Timed Access register controls the access to protected bits. To access protected bits, the
user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.
Now a window is opened in the protected bits for three machine cycles, during which the user can
write to these bits.
TIMER 2 CONTROL
Bit:
7
6
5
4
3
2
1
0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C / T2 CP / RL2
Mnemonic: T2CON
Address: C8h
TF2:
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is
equal to the capture register in down count mode. It can be set only if RCLK and TCLK are
both 0. It is cleared only by software. Software can also set or clear this bit.
EXF2: Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 overflow will
cause this flag to set based on the CP / RL2 , EXEN2 and DCEN bits. If set by a negative
transition, this flag must be cleared by software. Setting this bit in software or detection of a
negative transition on T2EX pin will force a timer interrupt if enabled.
RCLK: Receive Clock Flag: This bit determines the serial port 0 time-base when receiving data in
serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate generation, otherwise
timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode.
TCLK: Transmit Clock Flag: This bit determines the serial port 0 time-base when transmitting data in
modes 1 and 3. If it is set to 0, the timer 1 overflow is used to generate the baud rate clock
otherwise timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode.
EXEN2: Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if
Timer 2 is not generating baud clocks for the serial port. If this bit is 0, then the T2EX pin will
be ignored, otherwise a negative transition detected on the T2EX pin will result in capture or
reload.
TR2: Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clearing this bit will
halt the timer 2 and preserve the current count in TH2, TL2.
C / T2 : Counter/Timer Select. This bit determines whether timer 2 will function as a timer or a counter.
Independent of this bit, the timer will run at 2 clocks per tick when used in baud rate generator
mode. If it is set to 0, then timer 2 operates as a timer at a speed depending on T2M bit
(CKCON.5), otherwise it will count negative edges on T2 pin.
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Publication Release Date: February 1, 2007
Revision A7