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W25Q128BV_13 Datasheet, PDF (61/74 Pages) Winbond – 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
W25Q128BV
8.3 Power-up Timing and Write Inhibit Threshold(1)
Parameter
VCC (min) to /CS Low
Time Delay Before Write Instruction
Write Inhibit Threshold Voltage
Symbol
tVSL(1)
tPUW(1)
VWI(1)
spec
MIN
10
1
1.0
MAX
10
2.0
Note:
1. These parameters are characterized only.
VCC
VCC (max)
Program, Erase and Write Instructions are ignored
/CS must track VCC
VCC (min)
VWI
Reset
State
tVSL
Read Instructions
Allowed
tPUW
Device is fully
Accessible
Unit
µs
ms
V
VCC
Figure 38. Power-up Timing and Voltage Levels
/CS must track VCC
during VCC Ramp Up/Down
Time
/CS
Figure 43b. Power-up, Power-Down Requirement
Time
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Publication Release Date: October 03, 2013
Revision H