W9812G2IB Datasheet, PDF (6/43 Pages) Winbond – 1M × 4 BANKS × 32BITS SDRAM

6. BLOCK DIAGRAM
W9812G2IB
CLK
CKE
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
MODE
REGISTER
A0
AND
ADDRESS
EMRS
BUFFER
A9
A11
BS0
BS1
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
DATA
CONTROL
CIRCUIT
.
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DMn
DQ
BUFFER
DQ0
DQ31
DQMn
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE: The cell array configuration is 4096 * 256 * 32
Publication Release Date: Mar. 09, 2010
-6-
Revision A04