W9812G2IB Datasheet, PDF (16/43 Pages) Winbond – 1M × 4 BANKS × 32BITS SDRAM

W9812G2IB
9.5 AC Characteristics and Operating Condition
(VDD = 2.7V~3.6V, TA = 0 to 70°C for -6/-75, TA = -40 to 85°C for -6I/-6A) (Notes: 5, 6)
PARAMETER
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b) Command
Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
CLK Cycle Time
CLK High Level width
CLK Low Level width
Access Time from CLK
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
CL* = 2
CL* = 3
CL* = 2
CL* = 3
CL* = 2
CL* = 3
CL* = 2
CL* = 3
CL* = 2
CL* = 3
Power Down Mode Entry Time
Transition Time of CLK
(Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
Exit self refresh to ACTIVE command
*CL = CAS Latency
SYM.
t_RC
t_RAS
t_RCD
t_CCD
t_RP
t_RRD
t_WR
t_CK
t_CH
t_CL
t_AC
t_OH
t_HZ
t_LZ
t_SB
t_T
t_DS
t_DH
t_AS
t_AH
t_CKS
t_CKH
t_CMS
t_CMH
t_REF
t_RSC
t_XSR
-6/-6I/-6A
MIN. MAX.
60
42 100000
18
1
18
12
2
2
10 1000
6 1000
2
2
6
5
3
2
6
5
0
0
6
1
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
2
72
-75
UNIT
MIN. MAX.
65
45 100000 nS
20
1
t_CK
20
nS
15
2
t_CK
2
10 1000
7.5 1000
2.5
2.5
6
5.4
3
2
6
5.4
0
0
7.5 ^nS
1
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
64 mS
2
t_CK
75
nS
NOTES
8
8
9
9
7
9
8
8
8
8
8
8
8
8
- 16 -
Publication Release Date: Mar. 09, 2010
Revision A04