W9812G2IB Datasheet, PDF (15/43 Pages) Winbond – 1M × 4 BANKS × 32BITS SDRAM

W9812G2IB
9.3 Capacitance
(VDD = 2.7V~3.6V, f = 1 MHz, TA = 25°C)
PARAMETER
Input Capacitance
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE)
Input Capacitance (CLK)
Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested
SYM. MIN. MAX. UNIT
CI
-
CCLK
-
CIO
-
3.8
pf
3.5
pf
6.5
pf
9.4 DC Characteristics
(VDD = 2.7V~3.6V, TA = 0 to 70°C for -6/-75, TA = -40 to 85°C for -6I/-6A)
PARAMETER
SYM.
Operating Current
t_CK = min., t_RC = min.
Active precharge command cycling
without burst operation
Standby Current
t_CK = min, CS = VIH
VIH/L = VIH(min)/VIL(max.)
Bank: Inactive state
Standby Current
CLK = VIL, CS = VIH
VIH/L = VIH(min)/VIL(max)
Bank: Inactive state
No Operating Current
t_CK = min., CS = VIH(min)
Bank: Active state
(4 banks)
Burst Operating Current
t_CK = min.
Read/ Write command cycling
Auto Refresh Current
t_CK = min.
Auto refresh command cycling
Self Refresh Current
Self Refresh Mode
CKE = 0.2V
1 Bank operation
CKE = VIH
CKE = VIL
(Power Down mode)
CKE = VIH
CKE = VIL
(Power Down mode)
CKE = VIH
CKE = VIL
(Power Down mode)
IDD1
IDD2
IDD2P
IDD2S
IDD2PS
IDD3
IDD3P
IDD4
IDD5
IDD6
MAX.
-6/-6I/-6A -75
130
110
45
35
2
2
15
15
2
2
70
65
15
15
200
180
230
210
2
2
UNIT NOTES
3
3
3
mA
3, 4
3
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Publication Release Date: Mar. 09, 2010
Revision A04