W9825G2JB Datasheet, PDF (5/41 Pages) Winbond – 2M  4 BANKS  32BITS SDRAM

W9825G2JB
5. BALL DESCRIPTIONS
BALL LOCATION PIN NAME FUNCTION
DESCRIPTION
G8,G9,F7,F3,G1,G2,
G3,H1,H2,J3,G7,H9
A0A11
Address
Multiplexed pins for row and column address. Row
address: A0A11. Column address: A0A8. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
J7,H8
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
A1,A2,A8,A9,B1,B9,
C2,C3,C7,C8,D2,D3,
D7,D8,E2,E8,L2,L8,
M2,M3,M7,M8,N2,N3
DQ0DQ31
,N7,N8,P1,P9,R1,R2,
R8,R9
Data Input/
Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
J8
CS
Chip Select decoder is disabled, new command is ignored and
previous operation continues.
Command input. When sampled at the rising edge of the
J9
RAS
Row Address
Strobe
clock ^RAS , ^CAS and ^WE define the operation to be
executed.
K7
CAS
Column Address
Strobe
Referred to
RAS
K8
F2,F8,K1,K9
J1
J2
A7,F9,L7,R7
A3,F1,L3,R3
B2,B7,C9,D9,E1,L1,
M9,N9,P2,P7
B8,B3,C1,D1,E9,L9,
M1,N1,P3,P8,
E3,E7,H3,H7,K2,K3
WE
Write Enable _{Referred to} RAS
DQM03
The output buffer is placed at Hi-Z (with latency of 2) when
Input/output
mask
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with
zero
latency.
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
CKE
CKE controls the clock activation and deactivation. When
Clock Enable CKE is low, Power-down mode, Suspend mode, or Self
Refresh mode is entered.
VDD
Power
Power for input buffers and logic circuit inside DRAM.
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
VDDQ
Power for I/O Separated power from VDD, to improve DQ noise
buffer
immunity.
VSSQ
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
NC
No Connection No connection.
-5-
Publication Release Date: Apr. 11, 2011
Revision A01