W9825G2JB Datasheet, PDF (2/41 Pages) Winbond – 2M  4 BANKS  32BITS SDRAM

W9825G2JB
10.3 Control Timing of Input/Output Data.................................................................................. 19
10.4 Mode Register Set Cycle ................................................................................................... 20
11. OPERATING TIMING EXAMPLE................................................................................................. 21
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)........................................... 21
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)................ 22
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)........................................... 23
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)................ 24
11.5 Interleaved Bank Write (Burst Length = 8) ........................................................................ 25
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................. 26
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................... 27
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ........................................ 28
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ............................................. 29
11.10 Auto-precharge Write (Burst Length = 4) .......................................................................... 30
11.11 Auto Refresh Cycle............................................................................................................ 31
11.12 Self Refresh Cycle ............................................................................................................. 32
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) .................................. 33
11.14 Auto-precharge Timing (Read Cycle) ................................................................................ 34
11.15 Auto-precharge Timing (Write Cycle) ................................................................................ 35
11.16 Timing Chart of Read to Write Cycle ................................................................................. 36
11.17 Timing Chart of Write to Read Cycle ................................................................................. 36
11.18 Timing Chart of Burst Stop Cycle (Burst Stop Command) ................................................ 37
11.19 Timing Chart of Burst Stop Cycle (Precharge Command) ................................................ 37
11.20 CKE/DQM Input Timing (Write Cycle) ............................................................................... 38
11.21 CKE/DQM Input Timing (Read Cycle) ............................................................................... 39
12. PACKAGE SPECIFICATION ....................................................................................................... 40
13. REVISION HISTORY ................................................................................................................... 41
Publication Release Date: Apr. 11, 2011
-2-
Revision A01