W9812G2GH Datasheet, PDF (5/42 Pages) Winbond – a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words × 4 banks × 32 bits

W9812G2GH
5 PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
25-27, 60-66, 24,21 A0−A11
Address
Multiplexed pins for row and column address. Row
address: A0−A11. Column address: A0−A7. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
22,23
BS0, BS1 Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
2,4,5,7,8,10,11,13,74,
76,77,79,80,82,83,85,
31,33,34,36,37,39,40,
42,45,47,48,50,51,53,
54,56
DQ0−DQ31
Data Input/
Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
20
CS
Chip Select decoder is disabled, new command is ignored and
previous operation continues.
Command input. When sampled at the rising edge of the
19
RAS
Row Address
Strobe
clock, RAS , CAS and WE define the operation to be
executed.
18
CAS
Column
Address Strobe ^{Referred to RAS}
17
16,71,28,59
WE
DQM0~3
68
CLK
67
CKE
1,15,29,43
44,58,72,86
VDD
VSS
3,9,35,41,49,55,75,81 VDDQ
6,12,32,38,46,52,78,
84
14,30,57,69,70,73
VSSQ
NC
Write Enable _{Referred to RAS}
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with zero
latency.
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) Separated power from VDD, to improve DQ noise
for I/O buffer immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection
Publication Release Date: Aug. 13,2007
-5-
Revision A07