W83759A Datasheet, PDF (5/41 Pages) Winbond – ADVANCED VL-IDE DISK CONTROLLER

W83759A
PIN DESCRIPTION
SYMBOL PIN TYPE
DESCRIPTION
VL-Bus Interface
ADV
LCLK
100 I-PU Advanced mode indicator.
When high, chip is in W83759A mode. When low, chip is in
W83759 mode.
89
I VL-Bus clock.
SYSRST ⁹⁹
I System reset.
When active, the power-on setting pin acts as input.
LADS
IORDY
/ HDC
HMIO
HWR
BE2
BE0
95
I Address data strobe.
An active low input signal indicates that there is a valid address
and command on the bus.
98
I In W83759A mode: Enhanced IDE IORDY flow control input. Used
to throttle disk's PIO data transfers to improve PIO mode.
In W83759 mode: Host data or code status. Used to distinguish
between IO and interrupt or halt cycles.
97 I-PU Host memory or I/O status.
Used to distinguish between memory and I/O cycles.
96
I Host write or read status.
Used to distinguish between write and read cycles.
1
I Byte enable bits 2 and 0 from the host CPU address bus.
2
These active low inputs specify which bytes will be valid for host
read and write data transfers. When BE2 is low, the host performs
a 32-bit hard disk data transfer cycle when LDEV is active.
LDEV
92
O Local device.
An active low output signal which indicates that the current host
CPU command cycle is a valid W83759A I/O address (1F0h or
170h).
LRDY
93 Tri-O Local ready.
An active low output that indicates when a CPU transfer has been
completed. During a cycle LRDY will first be enabled and driven
high. When the cycle is completed, LRDY will immediately be
pulled low and will remain active for one T-state. Then it will drive
high for one T-state before finally being disabled to end the
sequence.
This signal is shared with all other VL-Bus targets and driven by
W83759A only during cycles W83759A has claimed as its own.
Publication Release Date: May 1995
-5-
Revision A1