W83759A Datasheet, PDF (33/41 Pages) Winbond – ADVANCED VL-IDE DISK CONTROLLER

W83759A
DC Characteristics, continued
PARAMETER
Operating Current
Standby Current
SYM.
IDD
ISTBY
CONDITIONS
FLCLK = 50 MHz
All input and I/O pins pulled high,
LCLK = VDD
MIN.
-
-
MAX.
25
800
UNIT
mA
µA
AC CHARACTERISTICS
All AC timing is measured from the 0.8V and 2.0V on the source signal to the 0.8V and 2.0V level on
the signal under test.
AC specifications are given for the following testing conditions:
VDD = 5V ± 5%, Temp. = 0° C to 70° C
VL-Bus shared signal loading = 100 pF
VL-Bus non-shared signal loading = 33 pF
ISA Bus signal loading = 240 pF
IDE device interface loading = 30 pF
SYMBOL
PARAMETER
MIN. MAX. UNIT
FIG.
t1
LCLK Period
20
-
nS Fig. 1
t2
LCLK High Time
5
-
nS Fig. 1
t3
LCLK Low Time
5
-
nS Fig. 1
t4
SYSRST Pulse Width
16
-
LCLK Fig. 1
t5
POS Pin to SYSRST Setup Time
200
-
nS Fig. 1
t6
POS Pin Hold Time from SYSRST
10
-
nS Fig. 1
t7
LADS to LCLK Setup Time
6
-
nS Fig. 2
t8
LADS Hold Time from LCLK
3
-
nS Fig. 2
t9
LDEV Active Delay from Address
39
nS Fig. 2
t10
VESA IO Read Host Data Drive Delay
5
16
nS Fig. 2, 4
t11
HMIO, HDC , HWR to LCLK Setup Time when ⁵
-
nS Fig. 2, 3
LDEV asserted at T2
t12
HMIO, HDC , HWR to LCLK Setup Time when ¹⁰
-
nS Fig. 2, 3
LDEV asserted at T2
t13
LRDY Active Delay from LCLK
5
16
nS Fig. 2, 3
t14
LRDY Inactive Delay from LCLK
6
18
nS Fig. 2, 3
t15
RDYRTN to LCLK Setup Time
6
-
nS Fig. 2, 3
t16
RDYRTN Hold Time from LCLK
3
-
nS Fig. 2, 3
t17
VESA IO Write Host Data Valid Delay
-
20
nS Fig. 3
t18
VESA IO Write Host Data Hold Time
0
-
nS Fig. 3, 5
- 33 -
Publication Release Date: May 1995
Revision A1