W83759A Datasheet, PDF (28/41 Pages) Winbond – ADVANCED VL-IDE DISK CONTROLLER

W83759A
FUNCTIONAL DESCRIPTION
Reset Initialization
The CPU clock rate, hard disk access time, hard disk controller enable, and hard disk I/O select are
latched at the rising edge of SYSRST . These values are used to control the host and drive access
signal timing. Additionally, the W83759A is initialized to a known state by an active low on SYSRST.
Any operation in progress is immediately terminated by SYSRST .
Host in Terface
The W83759A operates as a slave device, responding only to cycles within the host I/O address
space. The IDE drive data port at address 1F0h (170h) is a 16-bit port that requests a double-word
data transfer at address 1F0h (170h). All byte swapping, conversion, word, and double-word assembly
are done at the host interface. Table 1 summarizes the W83759A host interface cycle decoding.
Table 1. W83759A Cycle Definition
HMIO
HDC
HWR
ADDRESS SPACE
HOST BUS W83759A CYCLE
CYCLE
0
1
0
1F0h−1F7h and 3F6h
I/O Read IDE0 Read Cycle
0
1
1
1F0h−1F7h and 3F6h
I/O Write IDE0 Write Cycle
0
1
0
170h−177h and 376h
I/O Read IDE1 Read Cycle
0
1
1
170h−177h and 376h
I/O Write IDE1 Write Cycle
a. CPU WRITE CYCLES
Table 2. W83759A Write Data Operation
BYTE ENABLE
W83759A INPUT DATA
BE3
BE2
BE1
BE0 ^{HD[31:16] HD[15:0] SD[7:0]}
1
1
1
0
×
×
Valid
1
1
0
1
×
×
Valid
1
0
1
1
×
×
Valid
0
1
1
1
×
×
Valid
1
1
0
0
×
Valid
×
0
0
0
0
Valid
Valid
×
8-bit IDE Write Data Path:
CPU → Valid HD Byte → SD[7:0] → W83759A → ID[7:0]
16/32-bit IDE Write Data Path:
CPU → Valid HD Word → W83759A → ID[15:0]
I/O ADDRESS
1F1−1F7 (171−177)
1F0 (170)
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