W83759A Datasheet, PDF (35/41 Pages) Winbond – ADVANCED VL-IDE DISK CONTROLLER

W83759A
TIMING WAVEFORMS
All AC timing is measured from the 0.8V and 2.0V on the source signal to the 0.8V and 2.0V level on
the signal under test.
LCLK, SYSRST , Timing
LCLK
SYSRST
ENIDE, TEST
SP1, MD1, MD0
PRDYEN, SRDYEN
IDD[15:0], EMD1, EMD0
DMASL
t1
t2
t3
t4
t5
t6
Figure 1
Note: ENIDE, TEST, SP1, MD1, MD0, PRDYEN, SRDYEN, IDD[15:0], EMD1, EMD0, DMASL are POS (Power-On Setting)
pins. When SYSRST is low they are tri-stated as inputs.
VESA IO Read Timing
LCLK
LADS
HA[9:2],
BE2, BE0
HMIO = 0
HDC = 1
HWR = 0
LDEV
HD[31:0]
LRDY
RDYRTN
Local IDE Time
T1
T2
t7 t8
t11 _t12
t9
t10
t13
t14
t15 t16
Figure 2
Note: Local IDE cycle time is determined by SP1, MD1, and MD0 or by SP1, EMD1 and EMD0 at power-on. After power-on the
driver can program the timing register to tune the timing.
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Publication Release Date: May 1995
Revision A1