W9464G6IH Datasheet, PDF (46/54 Pages) Winbond – 1M × 4 BANKS × 16 BITS DDR SDRAM

11.13 Read Interrupted by Write & BST (BL = 8)
W9464G6IH
Burst Read cycle must be terminated by BST Command to avoid I/O conflict.
11.14 Read Interrupted by Precharge (BL = 8)
CLK
CLK
CMD
READ
PRE
CAS Latency = 2
DQS
DQ
CAS Latency
Q0 Q1 Q2 Q3 Q4 Q5
CAS Latency = 3
DQS
DQ
CAS Latency
Q0 Q1 Q2 Q3 Q4 Q5
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Publication Release Date:Mar. 17, 2010
Revision A04