W9464G6IH Datasheet, PDF (27/54 Pages) Winbond – 1M × 4 BANKS × 16 BITS DDR SDRAM

W9464G6IH
9.6 AC Characteristics and Operating Condition
SYM.
tRC
tRFC
tRAS
tRCD
tRAP
tCCD
tRP
tRRD
tWR
tDAL
tCK
tAC
tDQSCK
tDQSQ
tCH
tCL
tHP
tQH
tRPRE
tRPST
tDS
tDH
tDIPW
tDQSH
tDQSL
tDSS
tDSH
tWPRES
PARAMETER
-4
-5/-5I
-6/-6I
UNIT NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
Active to Ref/Active Command Period
55
55
60
Ref to Ref/Active Command Period
60
70
70
Active to Precharge Command Period
40 70000 40 70000 42 100000 nS
Active to Read/Write Command Delay Time 16
15
18
Active to Read with Auto-precharge Enable
16
15
18
Read/Write(a) to Read/Write(b) Command
Period
1
1
1
tCK
Precharge to Active Command Period
16
15
18
Active(a) to Active(b) Command Period
12
10
12
nS
Write Recovery Time
15
15
15
Auto-precharge Write Recovery + Precharge
Time
-
-
-
tCK
18
CL = 2
-
-
7.5 10 7.5
12
CLK Cycle Time
CL = 2.5
-
-
6
10
6
12
CL = 3
4
10
5
10
6
12
CL = 4
4
10
-
-
-
-
nS
Data Access Time from CLK, CLK
-0.65 0.65 -0.7 0.7 -0.7 0.7
16
DQS Output Access Time from CLK, CLK
-0.55 0.55 -0.6 0.6 -0.6
0.6
Data Strobe Edge to Output Data Edge Skew
0.4
0.4
0.4
CLk High Level Width
CLK Low Level Width
0.45 0.55 0.45 0.55 0.45 0.55
tCK
11
0.45 0.55 0.45 0.55 0.45 0.55
min
min,
min,
CLK Half Period (minimum of actual tCH, tCL)
(tCL,tCH)
(tCL,tCH)
(tCL,tCH)
nS
tHP
tHP
tHP
DQ Output Data Hold Time from DQS
-0.5
-0.5
-0.55
DQS Read Preamble Time
DQS Read Postamble Time
0.9 1.1 0.9 1.1 0.9
1.1
tCK
11
0.4 0.6 0.4 0.6 0.4
0.6
DQ and DM Setup Time to DQS, slew rate
0.5V/nS
0.4
0.4
0.4
DQ and DM Hold Time to DQS, slew rate
0.5V/nS
0.4
0.4
0.4
nS
DQ and DM Input Pulse Width (for each input) 1.75
1.75
1.75
DQS Input High Pulse Width
0.35
0.35
0.35
DQS Input Low Pulse Width
0.35
0.35
0.35
DQS Falling Edge to CLK Setup Time
0.2
0.2
0.2
tCK
11
DQS Falling Edge Hold Time from CLK
0.2
0.2
0.2
Clock to DQS Write Preamble Set-up Time
0
0
0
nS
- 27 -
Publication Release Date:Mar. 17, 2010
Revision A04