W9464G6IH Datasheet, PDF (26/54 Pages) Winbond – 1M × 4 BANKS × 16 BITS DDR SDRAM

W9464G6IH
9.5 DC Characteristics
SYM.
PARAMETER
MAX.
UNIT NOTES
-4 -5/-5I -6/-6I
Operating current: One Bank Active-Precharge; tRC = tRC
IDD0
min; tCK = tCK min; DQ, DM and DQS inputs changing once
per clock cycle; Address and control inputs changing once
130
120
115
7
every two clock cycles
Operating current: One Bank Active-Read-Precharge; Burst
IDD1 = 4; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA;
150 140 135
7, 9
Address and control inputs changing once per clock cycle.
IDD2P
Precharge Power Down standby current: All Banks Idle;
Power down mode; CKE < VIL max; tCK = tCK min; Vin =
VREF for DQ, DQS and DM
20
20
20
Idle standby current: CS > VIH min; All Banks Idle; CKE >
IDD2N ^{VIH min; tCK = tCK min; Address and other control inputs}
50
50
45
7
changing once per clock cycle; Vin > VIH min or Vin < VIL
max for DQ, DQS and DM
Precharge floating standby current: CS > VIH min; all banks
IDD2F _{idle; CKE > VIH min; address and other control inputs changing}
50
50
45
once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge quiet standby current: CS > VIH min; all banks
IDD2Q _{idle; CKE > VIH min; address and other control inputs stable} 50
50
45
at > VIH min or < VIL max; Vin = VREF for DQ, DQS and DM.
IDD3P
Active Power Down standby current: One Bank Active;
Power down mode; CKE < VIL max; tCK = tCK min; Vin =
VREF for DQ, DQS and DM
30
30
25
mA
Active standby current: CS > VIH min; CKE > VIH min;
One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min;
IDD3N _{DQ, DM and DQS inputs changing twice per clock cycle;}
60
60
60
7
Address and other control inputs changing once per clock
cycle
Operating current: Burst = 2; Reads; Continuous burst; One
IDD4R Bank Active; Address and control inputs changing once per 195 185 170
7, 9
clock cycle; CL=2; tCK = tCK min; IOUT = 0mA
Operating current: Burst = 2; Write; Continuous burst; One
IDD4W
Bank Active; Address and control inputs changing once per
clock cycle; CL = 2; tCK = tCK min; DQ, DM and DQS inputs
190
180
170
7
changing twice per clock cycle
IDD5 Auto Refresh current: tRC = tRFC min
210 210 210
7
IDD6
Self Refresh current: CKE < 0.2V; external clock on; tCK =
tCK min
2.5
2.5
2.5
Random Read current: 4 Banks Active Read with activate
every 20nS, Auto-Precharge Read every 20 nS; Burst = 4;
IDD7 tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing
330 320 300
twice per clock cycle; Address changing once per clock
cycle
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Publication Release Date:Mar. 17, 2010
Revision A04