W9464G6IH Datasheet, PDF (24/54 Pages) Winbond – 1M × 4 BANKS × 16 BITS DDR SDRAM

W9464G6IH
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
Voltage on I/O Pins Relative to VSS
VIN, VOUT
-0.5 ~ VDDQ +0.5
V
Voltage on Input Pins Relative to VSS
VIN
-1 ~ 3.6
V
Voltage on VDD Supply Relative to VSS
VDD
-1 ~ 3.6
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
-1 ~ 3.6
V
Operating Temperature (-4/-5/-6)
TOPR
0 ~ 70
°C
Operating Temperature (-5I/-6I)
TOPR
-40 ~ 85
°C
Storage Temperature
TSTG
-55 ~ 150
°C
Soldering Temperature (10s)
TSOLDER
260
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOUT
50
mA
Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
9.2 Recommended DC Operating Conditions
(TA = 0 to 70° C for -4/-5/-6, TA = -40 to 85°C for -5I/-6I)
SYM.
VDD
VDD
VDDQ
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
VICK (DC)
VID (DC)
VIH (AC)
VIL (AC)
VID (AC)
VX (AC)
VISO (AC)
PARAMETER
Power Supply Voltage (for -5/-6/-5I/-6I)
Power Supply Voltage (for -4)
I/O Buffer Supply Voltage (for -5/-6/-5I/-6I)
I/O Buffer Supply Voltage (for -4)
Input reference Voltage
Termination Voltage (System)
Input High Voltage (DC)
Input Low Voltage (DC)
Differential Clock DC Input Voltage
Input Differential Voltage.
CLK and CLK inputs (DC)
Input High Voltage (AC)
Input Low Voltage (AC)
Input Differential Voltage.
CLK and CLK inputs (AC)
Differential AC input Cross Point Voltage
Differential Clock AC Middle Point
MIN.
2.3
2.5
2.3
2.5
0.49 x VDDQ
VREF - 0.04
VREF + 0.15
-0.3
-0.3
0.36
VREF + 0.31
-
0.7
VDDQ/2 - 0.2
VDDQ/2 - 0.2
TYP.
2.5
2.6
2.5
2.6
0.50 x VDDQ
VREF
-
-
-
-
-
-
-
-
-
MAX.
2.7
2.7
2.7
2.7
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
-
VREF - 0.31
VDDQ + 0.6
VDDQ/2 + 0.2
VDDQ/2 + 0.2
UNIT
V
V
V
V
V
V
V
V
V
NOTES
2
2
2
2
2, 3
2, 8
2
2
15
V
13, 15
V
2
V
2
V
13, 15
V
12, 15
V
14, 15
Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS
Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
VIH (AC) and VIL (AC) are levels to change to the new logic state.
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Publication Release Date:Mar. 17, 2010
Revision A04