W9464G6IH Datasheet, PDF (4/54 Pages) Winbond – 1M × 4 BANKS × 16 BITS DDR SDRAM

W9464G6IH
1. GENERAL DESCRIPTION
W9464G6IH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 1M words × 4 banks × 16 bits. W9464G6IH delivers a data bandwidth of up to
500M words per second (-4). To fully comply with the personal computer industrial standard,
W9464G6IH is sorted into the following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the
DDR500/CL3 and CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I
grade which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the DDR333/CL2.5
specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
All Inputs reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9464G6IH is ideal for any high
performance applications.
2. FEATURES
• 2.5V ±0.2V Power Supply for DDR 333/400
• 2.6V ±0.1V Power Supply for DDR500
• Up to 250 MHz Clock Frequency
• Double Data Rate architecture; two data transfers per clock cycle
• Differential clock inputs (CLK and CLK )
• DQS is edge-aligned with data for Read; center-aligned with data for Write
• CAS Latency: 2, 2.5, 3 and 4
• Burst Length: 2, 4 and 8
• Auto Refresh and Self Refresh
• Precharged Power Down and Active Power Down
• Write Data Mask
• Write Latency = 1
• 15.6µS Refresh interval (4K/64 mS Refresh)
• Maximum burst refresh cycle: 8
• Interface: SSTL_2
• Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
Publication Release Date:Mar. 17, 2010
-4-
Revision A04