W49F002U Datasheet, PDF (4/23 Pages) Winbond – 256K X 8 CMOS FLASH MEMORY

W49F002U
operation if the boot block programming lockout feature is not activated. Once the boot block lockout
feature is activated, the whole chip erase function will erase the two main memory blocks and the two
parameter blocks but not the boot block. The device will automatically return to normal read mode
after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Sector Erase Operation
There are four sectors: two main memory blocks and two parameters blocks which can be erased
individually by initiating a six-byte command code sequence. Sector address is latched on the falling
edge of WE signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of WE
in this cycle. After the command loading cycle, the device enters the internal sector erase mode,
which is automatically timed and will be completed as fast as 100 mS (typical). The host system does
not require to provide any control or timing during this operation. The device will automatically return
to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect
the end of erase cycle.
When different sector address is loaded in the sixth cycle for sector erase command, the
correspondent sectors will be erased automatically; that these sections will be erased independedntly.
For detail sector to be erased information, please refer to the Table of Command Definition.
Program Operation
The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and
two parameter blocks and/or boot block from "0" to "1") is needed before programming.
The program operation is initiated by a 4-byte command code sequence (see Command Codes for
Byte Programming). The device will internally enter the program operation immediately after the byte-
program command is entered. The internal program timer will automatically time-out (50 µS max. -
TBP). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can
be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F002U is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F002U includes a data polling feature to indicate the end of a program or erase cycle.
When the W49F002U is in the internal program or erase cycle, any attempt to read DQ7 of the last
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle,
and become logical "1" or true data when the erase cycle has been completed.
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