W742E Datasheet, PDF (36/60 Pages) Winbond – 4 BIT MICROCONTROLLER

W742E/C811
T1
T2
T3
T4
Ins.
P0.0
rising latch
SIP R
1234 56 78
P0.0
falling latch
1234 56 78
Data latch
BUSYI
(PSR2.1)
EVF5
P0.1
NOTE: The serial clock frequency is fosc/2
Figure 5-12 Timing of the Serial Input Function (SIP R)
(2) When the SOP R instruction is executed, the data will be loaded to the serial output buffer (SOB)
from ACC and the RAM, the low nibble data of SOB is from ACC register and the high nibble data is
from RAM, and bit 3 of port status register 2(PSR2) will be set to "1" (BUSYO = 1). Then the P0.0
pin will send out 8 clocks or accept 8 clocks from external device and the data in SOB will be sent
out at the rising or falling edge of the P0.1 pin. After the 8 clocks have been sent, BUSYO will be
reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is
executed; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. Users can check the
status of PSR2.3 (BUSYO) to know whether the serial output process is completed or not. If a serial
output process is not completed, but the SOP R instruction is executed again, the data will be lost.
The timing is shown in Figure 5-13.
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