W742E Datasheet, PDF (30/60 Pages) Winbond – 4 BIT MICROCONTROLLER

W742E/C811
IEF.5 = 1 Interrupt 5 is accepted by Serial I/O signal
IEF.6 = 1 Interrupt 6 is accepted by a falling edge signal at port P1.3 (/INT1).
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
5.16.3 Port Enable Flag (PEF, P1EF)
The port enable flag is organized as 8-bit binary register (PEF.0 to PEF.7) and 4-bit register (P1EF.2
and P1EF.3). Before port RC, RD may be used to release the hold mode, the content of the PEF must
be set first. The PEFand P1EF are controlled by the MOV PEF, #I MOV P1EF,#I instructions. The bit
descriptions are as follows. Besides release hold mode, the RC port can be bit controlled individually to
perform interrupt function.
76543210
PEF w w w w w w w w
3210
P1EF w w -
-
Note: W means write only.
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.
PEF.4: Enable/disable the signal change at pin RD.0 to release hold mode.
PEF.5: Enable/disable the signal change at pin RD.1 to release hold mode.
PEF.6: Enable/disable the signal change at pin RD.2 to release hold mode.
PEF.7: Enable/disable the signal change at pin RD.3 to release hold mode.
P1EF.2: Enable/disable the falling edge signal at P1.2 to release hold mode.
P1EF.3: Enable/disable the falling edge signal at P1.3 to release hold mode.
5.16.4 Hold Mode Release Condition Flag (HCF, HCFD)
The hold mode release condition flag is organized as 8-bit binary register (HCF.0 to HCF.7) and
HCFD. It indicates which one releases the hold mode, and is set by hardware. The HCF can be read
out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold
mode will be released. But the HCFD can not be read, it is only for internal flag. It records the port RD
releasing the hold mode. The HCF and HCFD are set by hardware and clear by software. The HCF
and HCFD should be clear every time before enter the hold mode. When EVF, EVFD and HEF, HEFD
have been reset, the corresponding bit of HCF, HCFD is reset simultaneously. The bit descriptions are
as follows:
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