W742E Datasheet, PDF (22/60 Pages) Winbond – 4 BIT MICROCONTROLLER

W742E/C811
Fosc
Divider0
... Q1 Q2
Q9 Q10 Q11 Q12 Q13 Q14
S
EVF.0
Q
R
HEF.0
IEF.0
Hold mode release (HCF.0)
Divider interrupt
Option code is reset to "0"
1. Reset
2. CLR EVF,#01H
3. CLR DIVR0
SCR.2
Fosc/16384
Fosc/2048
Disable
Enable
WDT
Qw1 Qw2 Qw3 Qw4
R
R
R
R
Option code is set to "1"
Overflow signal
System Reset
1. Reset
2. CLR WDT
Figure 5-5 Organization of Divider0 and watchdog timer
5.12 Timer/Counter
5.12.1 Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TM0H),R instructions
are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to
0, and the specified value can be loaded into TM0. Then we can set MR0.3 to 1, that will cause the
event flag 1 (EVF.1) is reset and the TM0 starts to down count. When it decrements to FFH, Timer 0
stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag has
been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set
(HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as FOSC/1024 or FOSC/4
by setting MR0 bit 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure
5-6.
If the Timer 0 clock input is FOSC/4:
Desired Timer 0 interval = (preset value +1) × 4 × 1/FOSC
If the Timer 0 clock input is FOSC/1024:
Desired Timer 0 interval = (preset value +1) × 1024 × 1/FOSC
Preset value: Decimal number of Timer 0 preset value
FOSC: Clock oscillation frequency
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