W83195WG-382 Datasheet, PDF (17/27 Pages) Winbond – Winbond Clock Generator

W83195WG-382/W83195CG-382
5 DRI_CONT
4 Reserved
3 CPU2HTT_SYNC
2 AZSKEW<2>
1 AZSKEW<1>
0 AZSKEW<0>
STEPLESS FOR ATI K8 CLOCK GENERATOR
SRCT/ ATIG output state in during POWER
DOWN assertion.
1: Driven (2*Iref)
0: Tristate (Floating)
0 ^{SRCT/ ATIG output state in during STOP Mode}
R/W
assertion.
1: Driven (6*Iref)
0: Tristate (Floating)
Complementary parts always tri-state (floating) in
power down or stop mode.
1 Reserved
R/W
CPU align with HTT
1 1 : Enable
R/W
0 : Disable
1 _{CPU1 to HTT66 skew control.}
0 ^{Skew resolution is 300ps}
The decision of skew direction is same as
R/W
0 ^{ASKEW<2:0> setting}
7.17 Register 16: ( Default : 24h )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
7 INV_SRC
Invert the SRC phase
0 0: Default
1: Inverse
6 INV_PCI
Invert the HTT & PCI phase
0 0: Default
1: Inverse
5 CSKEW<2>
4 CSKEW<1>
3 CSKEW<0>
1 _{CPUCLKT1 to CPUCLKT0 skew control}
0
Skew resolution is 300ps
The decision of skew direction is same as
0 ^{CSKEW<2:0> setting}
2 PSKEW<2>
1 PSKEW<1>
0 PSKEW<0>
1 _{CPU1 to PCI skew control}
0
Skew resolution is 300ps
The decision of skew direction is same as
0 ^{PSKEW<2:0> setting}
TYPE
R/W
R/W
R/W
R/W
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Publication Release Date: Feb 2006
Revision 0.6