W83195WG-382 Datasheet, PDF (12/27 Pages) Winbond – Winbond Clock Generator

W83195WG-382/W83195CG-382
2 CLREQB0#_Ctr
1 PCIEN
0 HTTEN
STEPLESS FOR ATI K8 CLOCK GENERATOR
SRCCLK0 is controlled by the CLREQB# pin
0 _{1: Controllable}
R/W
0: Uncontrollable
PCI0 output control
1 _{1: Enable}
R/W
0: Disable
HTTCLK0 output control
1 _{1: Enable}
R/W
0: Disable
7.5 Register 4: ( Default : FEh)
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
7 Reserved
1 Reserved
6 Reserved
1 Reserved
5 Reserved
4 REFEN<2>
3 REFEN<1>
2 REFEN<0>
1 F48EN
0 Reserved
1 Reserved
PREF2 output control
1 1: Enable
0: Disable
PREF1 output control
1 1: Enable
0: Disable
PREF0 output control
1 1: Enable
0: Disable
PUSB48 output control
1 1: Enable
0: Disable
0 Reserved
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.6 Register 5: ( Default : 02h )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
7 Reserved
6 CNT_EN
PWD
FUNCTION DESCRIPTION
0 Reserved
Program this bit =>
1 : Enable Watchdog Timer feature.
0 : Disable Watchdog Timer feature.
Enable WD sequence =>
0 Program this bit to 1 firstly, then program the
Reg-20 to start the counting
Read-back this bit =>
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.
TYPE
R/W
R/W
Publication Release Date: Feb 2006
-8-
Revision 0.6