W19B320B Datasheet, PDF (15/51 Pages) Winbond – 32Mbit, 2.7~3.6-volt single bank CMOS flash memory

W19B320BT/B DATASHEET
toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erasure
operation. The system can read array data on DQ0-DQ7 on the following read cycle.
However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the system
should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed
the program or erasure operation. If it is still toggling, the device did not complete the operation, and the
system must write the reset command to return to reading array data.
Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status
as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks.
In this case, the system must start at the beginning of the algorithm while it returns to determine the status of
the operation.
6.3.5 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device
stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
Under both these conditions, the system must write the reset command to return to the read mode.
6.3.6 DQ3: Sector Erase Timer
After writing a sector erasure command sequence, the system may read DQ3 to determine whether erasure
has begun or not. (The sector erase timer does not apply to the chip erase command.) The entire time-out
applies after each additional sector erasure command if additional sectors are selected for erasure. Once the
timeout period has completed, DQ3 switches from “0” to “1.” If the time between additional sector erase
commands from the system can be assumed to be less than 50 μs, the system need not monitor, DQ3 does
not need to be monitored. Please also refer to Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of DQ7 (#Data Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3
is“1,” the Embedded Erase algorithm has begun; all further commands are ignored until the erase operation
is complete. If DQ3 is “0,” the device will accept additional sector erase commands.
The system software should check the status of DQ3 before and following each subsequent sector erase
command to ensure the command has been accepted. If DQ3 is high on the second status check, the last
command might not have been accepted.
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Publication Release Date:Dec, 22, 2008
Revisionv A5