W19B320B Datasheet, PDF (13/51 Pages) Winbond – 32Mbit, 2.7~3.6-volt single bank CMOS flash memory

W19B320BT/B DATASHEET
Any commands written during the chip erase operation will be ignored. However, a hardware reset shall
terminate the erase operation immediately. If this happens, to ensure data integrity, the chip erase
command sequence should be reinitiated when that bank has returned to reading array data.
6.2.7 Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiate the sector erase command
sequence, which is followed by a set-up command. Two additional unlock cycles are written, and are
then followed by the address of the sector to be erased, and the sector erase command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations are not required in system.
A sector erase time-out of 50 μs occurs after the command sequence is written. Additional sector
addresses and sector erase commands may be written during the time-out period. Loading the sector
erase buffer may be done in any sequence, and the number of sectors may be from one sector to all
sectors. The time between these additional cycles must be less than 50 μs; otherwise, erasure may
begin. Any sector erase address and command following the exceeded time-out may or may not be
accepted. To ensure all commands are accepted, processor interrupts be disabled during this time is
recommended. The interrupts can be re-enabled after the last Sector Erase command is written. Any
command other than Sector Erase during the time-out period resets the bank to the read mode. The
system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine whether or not the sector erase timer has timed out (See the
section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final #WE pulse
in the command sequence.
As the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses
are no longer latched. Please note that when the Embedded Erase operation is in progress, the system
can read data from the non-erasing bank at the same time. By reading DQ7, DQ6, DQ2, or RY/#BY in
the erasing bank, the system can determine the status of the erase operation. Please refer to the Write
Operation Status section for information on these status bits.
When the sector erase operation begins, no command is valid. All commands are ignored. However, a
hardware reset shall terminate the erase operation immediately. If this occurs, to ensure data integrity,
the sector erase command sequence should be reinitiated once the bank has returned to reading array
data.
6.3 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3,
DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or
erase operation is complete or in progress. The device also offers a hardware-based output signal,
RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
6.3.1 DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress
or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command
sequence.
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Publication Release Date:Dec, 22, 2008
Revisionv A5