W19B320B Datasheet, PDF (12/51 Pages) Winbond – 32Mbit, 2.7~3.6-volt single bank CMOS flash memory

W19B320BT/B DATASHEET
Once the Embedded Program algorithm is complete, the bank then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information.
Any commands written to the device during the Embedded Program Algorithm are ignored. Please note
that a hardware reset will immediately stop the program operation. The program command sequence
should be reinitiated when the bank has returned to the read mode, in order to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from “0” back to “1.” If trying to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6
status bits to indicate that the operation is successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can change “0” to “1.”
6.2.5 Unlock Bypass Command Sequence
The unlock bypass feature provides the system to program bytes or words to a bank which is faster
than using the standard program command sequence. The unlock bypass command sequence is
initiated by first writing two unlock cycles. And a third write cycle containing the unlock bypass
command, 20h, is followed. Then, the bank enters into the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. In the same manner, additional data is programmed. This mode dispenses with the
initial two unlock cycles which required in the standard program command sequence, resulting in faster
total programming time.
All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The system must issue the two-cycle unlock bypass reset command sequence to
exit the unlock bypass mode. The first cycle must contain the bank address and the data 90h. The
second cycle needs to contain the data 00h. Then, the bank returns to the read mode.
The device offers accelerated program operations by the #WP/ACC pin. When the V_HH is set at the
#WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle
Unlock Bypass program command sequence may be written. To accelerate the operation, the device
must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at
V_HH in any operation other than accelerated programming; otherwise the device may be damaged. In
addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent
behavior may occur.
6.2.6 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiate the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the bank returns to the read mode and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these status bits.
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Publication Release Date:Dec, 22, 2008
Revisionv A5