WCMB2016R4X Datasheet, PDF (6/11 Pages) Weida Semiconductor, Inc. – 128K x 16 Static RAM

Switching Waveforms
WCMB2016R4X
[12, 13]
Read Cycle No. 1(Address Transition Controlled)
t_RC
ADDRESS
DATA OUT
t_AA
t_OHA
PREVIOUS DATA VALID
[13, 14]
Read Cycle No. 2 (OE Controlled)
DATA VALID
ADDRESS
CE
OE
BHE/BLE
t_RC
t_ACE
t_DOE
t_LZOE
DATA OUT
V_CC
SUPPLY
CURRENT
t_DBE
t_LZBE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
DATA VALID
t_PD
t_HZCE
t_HZOE
t_HZBE
HIGH
IMPEDANCE
I_CC
50%
I_SB
Notes:
12. Device is continuously selected. OE, CE = V_IL, BHE and/or BLE = V_IL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE, BHE, BLE, transition LOW.
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