WCMB2016R4X Datasheet, PDF (5/11 Pages) Weida Semiconductor, Inc. – 128K x 16 Static RAM

WCMB2016R4X
Switching Characteristics Over the Operating Range^[8]
WCMB2016R4X
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t_RC
Read Cycle Time
70
ns
t_AA
Address to Data Valid
70
ns
t_OHA
Data Hold from Address Change
10
ns
t_ACE
CE LOW to Data Valid
70
ns
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Data Valid
OE LOW to Low Z^[9]
OE HIGH to High Z^{[9, 10]}
CE LOW to Low Z^[9]
CE HIGH to High Z^{[9, 10]}
35
ns
5
ns
25
ns
10
ns
25
ns
t_PU
CE LOW to Power-Up
0
ns
t_PD
CE HIGH to Power-Down
70
ns
t_DBE
BLE / BHE LOW to Data Valid
t_LZBE
BLE / BHE LOW to Low Z^[9]
5
t_HZBE
BLE / BHE HIGH to High Z^{[9, 10]}
WRITE CYCLE^[11]
70
ns
ns
25
ns
t_WC
Write Cycle Time
70
ns
t_SCE
CE LOW to Write End
60
ns
t_AW
Address Set-Up to Write End
60
ns
t_HA
Address Hold from Write End
0
ns
t_SA
Address Set-Up to Write Start
0
ns
t_PWE
WE Pulse Width
50
ns
t_BW
BLE / BHE LOW to Write End
60
ns
t_SD
Data Set-Up to Write End
30
ns
t_HD
Data Hold from Write End
0
ns
t_HZWE
WE LOW to High Z^{[9, 10]}
25
ns
t_LZWE
WE HIGH to Low Z^[9]
10
ns
Note:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V_CC(typ)/2, input pulse levels of 0 to V_CC(typ), and
output loading of the specified I_OL/I_OH and 30 pF load capacitance.
9. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZBE is less than t_LZBE, t_HZOE is less than t_LZOE, and t_HZWE is less than
t_LZWE for any given device.
10. t_HZOE, t_HZCE, t_HZBE and t_HZWE transitions are measured when the outputs enter a high impedence state.
11. The internal write time of the memory is defined by the overlap of WE, CE = V_IL, BHE and/or BLE =V_IL. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be
referenced to the edge of the signal that terminates the write.
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