W3E32M64S-XBX Datasheet, PDF (9/17 Pages) White Electronic Designs Corporation – 32Mx64 DDR SDRAM

White Electronic Designs
W3E32M64S-XBX
TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
DESELECT (NOP) (9)
NO OPERATION (NOP) (9)
ACTIVE (Select bank and activate row) (3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
CS#
RAS#
CAS#
H
X
X
L
H
H
L
L
H
L
H
L
L
H
L
L
H
H
L
L
H
L
L
L
L
L
L
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
WRITE ENABLE (10)
WRITE INHIBIT (10)
DM
DQs
L
Valid
H
X
WE#
ADDR
X
X
H
X
H
Bank/Row
H
Bank/Col
L
Bank/Col
L
X
L
Code
H
X
L
Op-Code
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined
(and should not be used) for READ bursts with auto precharge enabled and for
WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is non persistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each DDR SDRAM
requires AUTO REFRESH cycles at an average interval
of 7.8125µs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH commands can be posted to any given DDR
SDRAM, meaning that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during
the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered
and ends tRFC later.
SELF REFRESH*
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The SELF
July 2006
Rev. 3
9
White Electronic Designs Corporation • [phone] • www.wedc.com