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W3E32M64S-XBX Datasheet, PDF (15/17 Pages) White Electronic Designs Corporation – 32Mx64 DDR SDRAM | |||
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White Electronic Designs
50. ICC2N speciï¬es the DQ, DQS, and DM to be driven to a valid high or low logic level.
ICC2Q is similar to ICC2F except ICC2Q speciï¬es the address and control inputs to
remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is âworst case.â
51. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles before any READ command.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC voltage range of 2.6V ± 100mV.
W3E32M64S-XBX
July 2006
Rev. 3
15
White Electronic Designs Corporation ⢠(602) 437-1520 ⢠www.wedc.com
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