W3E32M64S-XBX Datasheet, PDF (1/17 Pages) White Electronic Designs Corporation – 32Mx64 DDR SDRAM

White Electronic Designs
W3E32M64S-XBX
32Mx64 DDR SDRAM
FEATURES
„ DDR SDRAM rate = 200, 250, 266, 333Mb/s
„ Package:
• 219 Plastic Ball Grid Array (PBGA),
25mm x 25mm, 625mm²
„ 2.5V ±0.2V core power supply
„ 2.5V I/O (SSTL_2 compatible)
„ Differential clock inputs (CK and CK#)
„ Commands entered on each positive CK edge
„ Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
„ Programmable Burst length: 2,4 or 8
„ Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
„ DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
„ DLL to align DQ and DQS transitions with CLK
„ Four internal banks for concurrent operation
„ Data mask (DM) pins for masking write data
(one per byte)
„ Programmable IOL/IOH option
„ Auto precharge option
„ Auto Refresh and Self Refresh Modes
„ Commercial, Industrial and Military
TemperatureRang es
„ Organized as 32M x 64
„ User configurable as 2x32Mx32 or 4x32Mx16
„ Pinout compatible with previous W3E16M64S-XBX
version.
„ Weight: W3E32M64S-XBX - 2.5 grams typical
BENEFITS
„ 41% SPACE SAVINGS vs. TSOP
„ Reduced part count
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
strobe transmitted by the DDR SDRAM during READs and
by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
* This product subject to change without notice.
July 2006
Rev. 3
1
White Electronic Designs Corporation • [phone] • www.wedc.com